This invention relates to semiconductor fabrication, and particularly to methods of activating dopants using multiple consecutive millisecond-range anneals.
There are ongoing efforts to reduce the dimensions and increase the density of integrated circuit features. Modern integrated circuits (ICs) can include various types of active components such as n-type and p-type field effect transistors (NFETs and PFETs) as well as passive components such as resistors, diodes, electrical fuses, etc. The performance and variability of these components depend on the ability to uniformly activate dopants in semiconductor materials across different microstructures. Due to ongoing efforts to reduce the dimensions and increase the density and complexity of integrated circuit features, there is a continued need to increase the activation of such dopants without inducing excessive diffusion thereof. It is also desirable to maintain a high level of dopant activation across different devices and microstructures.
One specific example of the use of dopants is in the gate conductor and the source and drain regions on opposite sides of the channel of a MOSFET (metal oxide semiconductor field effect transistor) device. As MOSFET devices are scaled down to less than 100 nanometers in gate or channel length, highly doped, shallow source and drain extension regions can be employed to achieve high drive current capability. Currently, shallow source and drain extension regions are formed through the ion implantation of dopants into a semiconductor substrate near its surface on opposite sides of the gate conductor. The dopants are then activated by conducting laser annealing or other millisecond-scale annealing of the implanted extension regions either prior, during, or after a Rapid Thermal Anneal (RTA).
Laser annealing of semiconductors has been widely known in the art for the past several decades. However, up until very recently, it has not been employed in the fabrication of CMOS-based logic and memory ICs due to its large pattern effects, i.e., the sensitivity of laser energy coupling to layout patterns of various microstructures. These large pattern effects can lead to a highly non-uniform heating of various electrical devices and associated microstructures present on the wafer surface. Laser annealing can be characterized by the duration of exposure to its radiation. Pulsed lasers operate in a nanosecond-range regime with exposure durations of tens to hundreds of nanoseconds. At such short anneals, thermal activation of dopants can be inefficient. Consequently, the dopant activation process relies on a phase transition such as melting-recrystallization or solid phase epitaxial (SPE) re-growth of amorphized and doped semiconductors. Due to this reason, nanosecond-scale laser annealing is also referred to as melt laser annealing or pulsed laser annealing. Nanosecond-scale laser annealing has a very large temperature pattern effect because the laser energy absorbed in surface microstructures does not have sufficient time to spread uniformly within the substrate via thermal diffusion. In addition to large pattern effects, its reliance on inducing phase transitions in microstructures produces substantially different levels of dopant activation near exposure edges or in areas of exposure overlap. Nanosecond-scale laser annealing is usually operated in a step-and-repeat mode where a small portion of the wafer surface (typically entire IC rectangular die) is exposed to a pulse at once, followed by a step-and-repeat process to cover the entire wafer surface. This places undesirable areas of exposure overlap or exposure perimeter into the dicing channels that are not electrically usable.
In contrast, millisecond-scale laser annealing has exposure times ranging from several microseconds to tens of milliseconds. In this range, thermal activation of dopants can be efficient, and the concentration of active dopants is proportional to the peak anneal temperature. Continuous wave lasers are employed in this regime. Since the laser beam is shaped in the form of a line, the wafer surface is raster scanned, which means that it is scanned as a pattern of parallel lines or curves. In this case, the exposure time (also referred to as the dwell time) is equal to the characteristic beam width in the scanning direction (often defined at full width at half maximum (FWHM)) divided by the scan speed. The beam length (e.g., about 10 millimeters (mm)) perpendicular to the scanning direction (often defined at full width at 95-99% of the maximum) is usually much smaller than the wafer size (e.g., about 300 mm). As such, adjacent scans (also referred to as exposures) are often applied with some overlap to completely cover the entire wafer surface. In the overlap region, the wafer surface is exposed and annealed twice. Successful application of millisecond-scale laser annealing in IC fabrication depends on whether the overlap region has substantially the same properties as singly annealed regions. In contrast to nanosecond-scale laser annealing, this appears to be true for source and drain activation processes since common dopants undergo little diffusion during laser annealing and their activation depends on the peak anneal temperature in the absence of or after any phase transition processes in the doped material (e.g., after SPE process). Pattern effects can be reduced in millisecond-scale laser annealing by, for example, allowing more time for absorbed laser energy (i.e., heat) to evenly spread in the substrate via thermal diffusion.